The present invention relates to a subscriber line interface circuit in an asynchronous transfer mode switching system, and particularly to a packet communication signal processing circuit for assembling and disassembling packets and processing voice signals and to a digital signal processor employed in a packet communication switching system. Diversified media having different speeds and protocols, such as audio, data, viedo and the like, can be switched and processed by packet communication to realize a multimedia communication system. Voice and video signals have characteristics which vary momentarily in the quantity of information they carry, and hence the amount of information transmitted can be varied dynamically in response to the characteristics of the signals to achieve transmission with high efficiency.
Voice signals in a packet communication network will be described with reference to FIG. 1.
The voice signal from an analog phone 1 is transmitted via a subscriber line 2 to a switching system 3, composed of a subscriber line interface circuit 3a and a switch circuit 3b. The voice analog signal is assembled as a packet at the subscriber line interface circuit 3a and an output from the switch circuit 3b to a high speed digital line 4. The packet assembled at the switching system 3 serving the calling party is transmitted to a switching system 3 serving the called party by way of a plurality intermediate switching stations 5. The packet is then disassembled to reproduce the voice analog signal, which is supplied to the analog phone 1 of the called party.
The format of the packet is illustrated in FIG. 2.
The packet format PAC provides for a header HEA and an information portion INF. The header HEA is composed of the address of the called party and the properties of the packet. The information portion INF is composed of pulse-code modulated voice data (e.g. CCITT recommendation G711, G721).
The basic arrangement of a conventional subscriber circuit in a switching system 3 will be described with reference to FIG. 3. The subscriber line interface circuit package accomodates m number of subscriber lines.
The subscriber line interface circuit package 10 comprises a microprocessor 11, a buffer memory 12, a direct memory access controller DMAC 13, a switch interface circuit SWINF 14, a bus arbitrary circuit BUSARB 15, an internal common bus 16, a clock generator 17, a plurality of line terminal circuits 18.sub.1 - 18.sub.m (m in number in this case, hereinafter referred to as BORSCHETs) and a plurality of digital signal processors DSP 19.sub.1 -19.sub.m (m in number in this case).
Each of the BORSCHTs 18.sub.1 -18.sub.m is connected to each of subscriber lines 20.sub.1 -20.sub.m. In detail, a BORSCHT comprises a battery feed circuit, an ovevoltage protection circuit, a ring circuit, a supervision circuit, a coding-decoding circuit, a hybrid circuit and a testing circuit. Analog voice signals supplied by the subscriber lines 20.sub.1 to 20.sub.m are converted to PCM voice signals which are supplied to the digital signal processors 19.sub.1 -19.sub.m. Similarly, PCM voice signals supplied by the digital signal processors 19.sub.1 - 19.sub.m are converted to the analog signals which are supplied to the subscriber lines 20.sub.1 to 20.sub.m. The battery feed circuit, the ring circuit, and the supervision circuit are operated under the control of the microprocessor 11. Each of the digital signal processors 19.sub.1 - 19.sub.m serves to assemble or disassemble packets and subjects voice signals to various signal processings. The digital signal processors 19.sub.1 - 19.sub.m supply the packets assembled inside thereof to the buffer memory 12 by way of the internal common bus 16, and hence the assembled packets are stored in the buffer memory 12. The microprocessor 11 is informed of the storage of the assembled packets in the buffer memory 12. On the other hand, when a packet is received by the subscriber line interface circuit package 10, the digital signal processors 19.sub.1 to 19.sub.m are informed of the reception of the packet by the microprocessor 11. The digital signal processors 19.sub.1 - 19.sub.m, after being informed of the reception of the packet, extract the received packet from the buffer memory 12.
The buffer memory 12 temporarily stores the packet data at the time when the packet data is transferred between the data signal processors 19.sub.1 - 19.sub.m and the switch interface circuit 14. The switch interface circuit 14 interfaces between the switch circuit and the buffer memory 12. The direct memory access controller 13 serves to control data transfer between the buffer memory 12 and the switching interface circuit 14 upon reception of an instruction from the microprocessor 11. The bus arbitrary circuit 15 is a contention control circuit for transferring the data in the subscriber line package 10 by way of the internal common bus 16.
The microprocessor (central processing unit) 11 subjects the digital signal processor 19.sub.1 -19.sub.m and the BORSCHTs 18.sub.1 to 18.sub.m to various call progresses and controls the transfer of packet data between the switching interface circuit 14, the buffer memory 12 and the digital signal processors 19.sub.1 - 19.sub.m.
FIG. 4 is a view showing the process of generation and transmission of packets by the subscriberline interface circuit 10.
The analog voice signal generated at the terminal on the transmitting side is illustrated in FIG. 4(A). As is evident from the waveform in FIG. 4(A), voice periods and silence periods are mixed. The digital signal processor 19 in the subscriber line interface circuit of the calling party identifies voice or silence periods in the analog voice signal. Only the signal during the voice periods is packetized, as illustrated in FIG. 4(B). The voice period units are identified as Tn (n is 1, 2, . . . 5); It is recognized that about 50% of a call between subscribers, on the average is in a non-conversation state. Hence, compressing the silence periods promotes the efficient use of the lines of the packet switched network (asynchronous communication network) and the packet switch circuit.
The buffer memory stores voice data at least for one packet to permit the voice periods to be discriminated or distinguished from the silence periods. That is, a voice or silence period is discriminated after the voice data for one packet is stored, and the stored packet is discarded in the case of a silence period. A near-end echo genereted by the hybrid circuit in a BORSCHT 18 can be cancelled by the digital signal processor 19. Furthermore, to code the voice signal for reducing the information quantity, the voice signal can be subjected to a voice band-width compression signal processing procedure and an adaptive differential PCM signal or the like can be used.
As is evident from a comparison of FIG. 4(B) and FIG. 4(C), the receiving or addressed packets P1r, P2r, . . . do not arrive at given intervals due to delay variations even if the sending or addressing packets P1, P2, . . . are transmitted at given intervals. Each packet is subjected to queuing control when it passes the switch circuit in a packet switched network, and the queuing time is momentarily varied in response to the traffic carried by the packet switched network. Moreover, packets do not always pass along the same intermediate route when they are transmitted from the subscriber line interface circuit at the calling party to that of the called party. To absorb the delay variations, it is effective to store the packets in the buffer memory. However, the following problems in the subscriber line interface circuit occur.
A sampling clock signal used in the coding decoding circuit in the BORSCHTs 18.sub.1 to 18.sub.m is asynchronous with respect to the frequency generated by the clock generator 17 for supplying a system clock signal to each digital signal processor 19.sub.1 to 19.sub.m. This reduces the signal-to-noise ratio (S/N ratio) both in the analog/digital and the digital/analog conversions.
In the coding circuits of the BORSCHTs 18.sub.1 to 18.sub.m, the analog signal is converted to .mu.-law PCM data or A-law PCM data (CCITT recommendation G7ll) as a logarithmic compression code which is converted to a linear code in the digital signal processors 19.sub.1 to 19.sub.m. The analog signal is not directly converted to the linear code as set forth above, which reduces the deterioration of the S/N ratio.
The data transfer in the subscriber line interface circuit package 10 involves the buffer memory 12, the direct memory access controller 13, and the bus arbitrary circuit 15, which enlarges the scale of the subscriber circuit
Furthermore, the control of the BORSCHTs 18.sub.1 to 18.sub.m by the microprocessor 11 involves a register for holding a control signal supplied by the microprocessor 11, which enlarge the scale of the subscriber line circuit.
Additionally, a complicated process is needed to transfer the data in the subscriber line interface circuit package 10, namely, two stages transfer from or to the buffer memory 12, which lowers the effective processing capacity of the digital signal processors 19.sub.1 to 19.sub.m.